1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a delay drift compensation circuit that compensates for delay drift caused by temperature and voltage variations in a clock tree.
2. Description of the Related Art
In general, high-speed memory devices, such as synchronous DRAMs, operate in synchronization with an external clock signal. As the speed of clock signals has continued to increase with advances in semiconductor fabrication techniques, delay-locked loops (DLLs) or phase-locked loops (PLLs) have been used to reduce skew (time offset) between clocks.
A DLL receives a reference clock signal from an external source, generates an internal clock signal and synchronizes it to the reference clock signal, and provides the internal clock signal to an input and output circuit of a memory device. A conventional DLL includes a clock driver and a phase detector. The time required for transmitting the internal clock signal from an output port of the clock driver to an input port of the phase detector is referred to as feedback path delay. The time required for transmitting the internal clock signal from an output port of the clock driver to the input and output circuit is referred to as clock distribution path delay. It may be preferable that the feedback path delay be equal to the clock distribution path delay.
A clock distribution path is generally long. To make the feedback path delay equal to the clock distribution path delay, the feedback path and clock distribution path can be designed to be the same length. However, a long feedback path increases the layout area of a DLL and the power consumption of a clock driver. The increased power consumption of the clock driver can considerably deteriorate a noise environment of the DLL.
The feedback path delay may be increased to equal the clock distribution path delay, for example, by reducing the feedback path length and by installing a loading capacitor on the feedback path. However, the feedback path delay can differ from the clock distribution path delay due to temperature and voltage variations in the clock tree.
For example, as the temperature increases, the clock distribution path delay increases, because the resistance of the clock distribution path increases with temperature. However, the increase in feedback path delay may not be proportional to the increase in the clock distribution path delay. The phase of the internal clock signal generated by the DLL may undesirably drift with temperature and voltage variations in the clock tree.